The increasing demand for higher density and performance in integrated circuits has spurred the evolution of 3D architectures, which rely heavily on TSVs for vertical interconnectivity. However, copper—the incumbent material for TSV metallization—faces severe constraints as device dimensions shrink, including limited barrier layer effectiveness, diffusion risks, and oxidation vulnerabilities. To circumvent these limitations, the team focused on ruthenium, a noble metal distinguished by its inherent oxidation resistance and barrier-free compatibility, making it exceptionally suited for high-aspect-ratio nanoscale through-silicon structures.

Central to their technological breakthrough is a meticulously engineered multi-step etching technique leveraging fluorine radicals and oxygen gases. This process enables the fabrication of tapered n-TSV arrays with unprecedented aspect ratios as high as 10.4:1, maintaining critical dimensions down to an extraordinary 39 nanometers. The tapering not only enhances mechanical stability but also ensures superior uniformity and electrical performance across ultra-dense TSV arrays, a necessity for reliable power delivery in advanced 3D ICs.

Following precise silicon etching, the team utilized atomic layer deposition (ALD) to achieve a conformal, void-free deposition of pure ruthenium within the n-TSV cavities. This method effectively eliminates the need for traditional diffusion barrier layers, resulting in an impressive resistivity of 19.9 micro-ohm centimeters for the ruthenium fill—an attribute that underscores the metal’s superior electrical conductivity and reliability under nanoscale confinement.

Innovation extended to post-deposition processing, where a novel dry recess etching protocol based on chlorine and oxygen plasma chemistry was established. This step selectively removes metallic residues from the sidewalls of the TSVs with a ruthenium-to-liner oxide etch selectivity ratio exceeding 50:1. Such precision ensures the integrity of the sidewall dielectric and the elimination of parasitic conductive pathways, which could otherwise compromise device performance and longevity.

Complementing the metallization and etching advances, the researchers implemented an extreme all-dry thinning scheme to prepare SOI wafers. By utilizing the buried oxide layer as a highly reliable etch stop, they achieved wafer thinning down to a top silicon thickness of 500 nanometers, sustaining total thickness variation below 15 nanometers across 200-mm wafers. This rigorous dimensional control is critical for uniform device performance and facilitates the integration of BSPDNs without damaging the delicate TSV structures.

A plasma-assisted all-dry backside reveal technique further exposed the embedded nano TSVs while famously preserving the integrity of the sidewall dielectric liner with less than 1-nanometer loss. This capability offers significant advantages in process control and minimizes potential leakage currents or dielectric breakdown points at the TSV interfaces.

Electrical characterization of the pure ruthenium-filled n-TSVs demonstrated outstanding performance metrics. The average line resistance was measured at 29 ohms per micrometer, indicating exceptional conductivity even at the nanoscale. Reliability tests involving 100 thermal cycles between −40 °C and 125 °C exhibited less than a 1% relative change in resistance, highlighting the robust thermal stability of these interconnects under typical operating environments.

Leakage current assessments reflected similarly encouraging results. Under a 6 V bias, leakage currents remained below 80 picoamperes in dense TSV arrays, and breakdown voltages exceeded 9 V with leakage currents under 0.2 nanoamperes. These findings confirm the dielectric liner’s effectiveness and the TSVs’ ability to withstand high electric fields without degradation or failure.

Notably, accelerated electromigration testing underscored the pure ruthenium n-TSVs’ durability, with time-to-failure metrics consistent with long-term operational stability. This resilience is especially significant as electromigration remains a dominant failure mode in nanoscale metal interconnects, often limiting device lifespan in advanced semiconductor technologies.

Altogether, this integrated process presents a viable and scalable manufacturing pathway for the realization of backside power-delivery networks. By merging novel material selection with precise process engineering—ranging from nano-fabrication to wafer thinning—the approach addresses critical bottlenecks hindering power delivery at sub-3 nm technology nodes, all while paving the way for energy-efficient and high-performance 3D integrated circuits.

This landmark study, titled “Pure Ru n-TSV Processing and Extreme All-Dry SOI Wafer Thinning for a Backside Power-Delivery Network,” represents a significant stride in semiconductor innovation, unlocking new horizons for 3D power delivery architectures. The research was conducted by Biao Wang, Feifeng Huang, Qiancheng Wang, Zhao Chen, Hongbin Chen, Quan Wang, Qiu Shao, Yiqin Chen, Zhengyuan Wu, Bo Feng, Ming Ji, and Huigao Duan, and published in the journal Engineering.

For researchers and engineers aiming to transcend the limitations of copper in TSV technologies, this study not only offers a fundamental material innovation but also a comprehensive set of process strategies critical for next-generation semiconductor device fabrication. The all-dry approach minimizes contamination and mechanical stresses, while the ruthenium-based metallization ensures corrosion resistance, electrical reliability, and scalability to the nanoscale dimensions demanded by emerging technology nodes.

The implications of this work stretch beyond just power delivery; integrating such high-aspect-ratio, pure metal TSVs could revolutionize chip stacking and heterogeneous integration, enabling faster, more efficient devices with smaller footprints and lower parasitic losses. As the semiconductor industry relentlessly pursues scaling and performance improvements, adopting such advanced materials and processes will be pivotal in meeting the ever-increasing demands of computing and communication systems.

In summary, this research heralds a promising future for backside power delivery networks, through a synthesis of ruthenium metallization and precise, ultra-thin wafer engineering. Its impact is poised to resonate across the semiconductor landscape, influencing design paradigms and manufacturing protocols alike.

Subject of Research: Advanced nano through-silicon via (n-TSV) fabrication and silicon-on-insulator (SOI) wafer thinning techniques for backside power-delivery network integration in 3D integrated circuits.

Article Title: Pure Ru n-TSV Processing and Extreme All-Dry SOI Wafer Thinning for a Backside Power-Delivery Network

News Publication Date: 4-Apr-2026

Web References:

• Full article: https://doi.org/10.1016/j.eng.2025.10.026
• Journal website: https://www.sciencedirect.com/journal/engineering

Image Credits: Biao Wang, Feifeng Huang et al.

Keywords

Ruthenium, nano through-silicon vias, TSV, silicon-on-insulator, SOI wafer thinning, backside power-delivery network, 3D integrated circuits, atomic layer deposition, dry etching, high aspect ratio, nanoscale metallization, electromigration.

The focus of this research is primarily on the etching process, which involves creating deep, narrow holes in alternating layers of silicon-based materials. The precision required for these holes is critical; they must not only be deep and narrow but also have smooth surfaces to ensure optimal functionality in memory operations. Traditional methods often struggle with producing the ideal hole shape and depth, but innovative approaches using plasma have emerged to address these challenges. Through public-private partnerships, researchers aim to investigate and refine these methods, significantly impacting how data is stored in electronic devices.

These developments underscore the urgency for innovations in data storage technologies, driven by the proliferation of artificial intelligence and big data applications. As the demand for data storage grows exponentially, the evolution of 3D NAND flash memory stands as a beacon of progress. By stacking memory cells—a technique analogous to transforming a single-story house into a multi-floor apartment—significant amounts of additional data can be accommodated within the same physical footprint. The exploration of new etching techniques thus represents a pivotal area of focus in this ongoing quest for denser storage solutions.

A critical advancement in this domain involves reactive ion etching, a process that utilizes plasma as a mechanism to carve out the necessary holes within the silicon oxide and nitride layers. The fundamental principle here relies on the interaction between the ionized particles in the plasma and the atoms within the semiconductor materials, which facilitates the etching process. However, the nuances of this reaction are not yet fully understood, prompting researchers to dive deeper into the mechanics of reactive ion etching to identify ways to boost efficiency.

One of the leading areas of exploration is cryo etching, characterized by maintaining the semiconductor wafer at lower temperatures during the etching process. This innovative approach has produced favorable results compared to traditional methods. By employing hydrogen fluoride gas in conjunction with plasma, a notable increase in the etching rate has been observed, allowing researchers to carve the necessary holes more quickly and efficiently. The implications of this discovery extend beyond mere speed; it also enhances the overall quality of the etching process, which is imperative for developing superior memory chips.

In recent experiments, researchers found that using hydrogen fluoride plasma rather than separate hydrogen and fluorine gases doubled the etching rates for silicon oxide and silicon nitride. Such findings are groundbreaking, indicating not only an increase in efficiency but also an improvement in the structural integrity of the etched materials. Enhanced etching quality mitigates potential performance issues in the final product, thereby elevating the reliability of future memory devices.

Phosphorus trifluoride was another crucial element examined during the research. This compound is traditionally recognized for its role in etching silicon dioxide and, through experimentation, it was revealed to significantly boost etching rates. The researchers confirmed that its application quadrupled the etching speed of silicon dioxide while minimally affecting that of silicon nitride. The implications of these results stress the importance of understanding the various components involved in the etching process and how each can be manipulated to achieve optimal outcomes.

Moreover, the research unveiled an interesting intersection between water and ammonium fluorosilicate—compounds that play a role during the etching. Water was shown to weaken the bonds formed by ammonium fluorosilicate, facilitating a more efficient etching process. By identifying and leveraging these interactions, researchers are laying the groundwork for novel methods capable of improving the overall efficiency and effectiveness of semiconductor manufacturing.

The collaborative nature of this research serves as a paradigm for various sectors within the scientific community. By merging expertise from academia, industry, and national labs, the undertaking epitomizes how shared knowledge can yield significant advances in technology. This initiative not only yields insights into microelectronics but also fosters teamwork with a focus on addressing critical challenges facing the field overall. As researchers work together, they build essential bridges that can lead to further advancements in semiconductor technology.

At its core, the quest for optimizing 3D NAND flash technology is emblematic of broader industry trends. The drive for denser data storage directly aligns with the accelerating needs of modern technology, where efficient memory solutions become more than conveniences—they become necessities. As artificial intelligence, data analytics, and connected devices proliferate, the significance of effective data storage solutions cannot be overstated. This research is a crucial step towards meeting those needs.

In summary, the study conducted by these esteemed institutions not only sheds light on the intricacies of semiconductor etching processes but also highlights critical advancements that will define the future of digital memory. As researchers continue to innovate and refine their methods, the prospects for enhancing data storage capabilities look promising. The intersection of science, technology, and collaboration is paving the way for unprecedented growth in how we think about and utilize memory in electronic devices.

The significance of this research cannot be overlooked; it represents an ongoing commitment to solving some of today’s most challenging technology problems. The implications extend far beyond individual projects, paving the way for new possibilities across various fields, including communications, computing, and data science. The evolving landscape of microelectronics is witnessing a rebirth, and this collaborative endeavor is a cornerstone of its future.

With organizations like the Princeton Plasma Physics Laboratory driving such transformative work, the future of data storage and semiconductor technology appears increasingly robust and capable of meeting the challenges of a fast-paced digital world. Research such as this lays the groundwork for innovations that could redefine our technological foundations, ensuring a steady, forward momentum in our quest for greater efficiency and efficacy in digital memory.

Subject of Research: 3D NAND Flash Memory Manufacturing
Article Title: Low-temperature etching of silicon oxide and silicon nitride with hydrogen fluoride
News Publication Date: 18-Nov-2024
Web References: Princeton Plasma Physics Laboratory, Lam Research
References: Journal of Vacuum Science & Technology A
Image Credits: Kyle Palmer / PPPL Communications Department

Keywords