The research, published in Frontiers in Electronics, presents a complete analog hardware implementation of an artificial neuron built on adiabatic logic principles. Unlike traditional CMOS circuits powered by a fixed DC supply, adiabatic circuits use a gradually alternating AC power supply that periodically returns stored capacitive charge back to the source. This charge-recovery approach means that much of the energy invested in each computation is reclaimed rather than dissipated as heat, a property that becomes enormously valuable when the same operation must be repeated billions of times per second across large networks.

The core of the new design is a Double-Tree Single-Clock architecture comprising two capacitive trees driven by a single sinusoidal power clock. Twelve one-bit capacitive synapses are implemented in 0.18-micrometer CMOS technology, and crucially the design supports both positive and negative synaptic weights. Positive weights are mapped onto one capacitive tree and negative weights onto the other, allowing the hardware to reproduce the full mathematical behavior of a software-defined neuron, including its bias term. Single-pole double-throw switches steer charge onto or away from each synapse capacitor in synchrony with the slowly varying power clock, so that during the rising phase charge flows in and during the falling phase it flows back out to the power clock generator.

This differential two-tree structure produces two sinusoidal membrane voltages at the inputs of a threshold logic circuit, which implements the neuron’s binary activation function. When the positive-tree membrane voltage exceeds the negative-tree voltage at the sampling moment, the comparator outputs a logic one; otherwise it outputs zero. Because the two trees respond identically to fluctuations in the power clock, the differential arrangement inherently cancels common-mode errors, a significant robustness improvement over the team’s earlier single-tree adiabatic capacitive artificial neuron, which relied on a fixed absolute DC threshold and was vulnerable to power-clock variations.

A major innovation in the new work is the redesigned threshold logic circuit itself. Conventional threshold logic implementations suffer from large propagation delays and can latch incorrect data when voltage headroom is limited. The Edinburgh team’s solution is a two-stage design combining a dynamic latch clocked comparator with a novel clocked set-reset latch. During the pre-charge phase, the comparator output nodes are reset and the supply-to-ground path is cut off, while the latch holds the previous state to provide a stable output. During the comparison phase, the comparator resolves the differential membrane voltages and the clocked latch cleanly captures the result, suppressing premature regeneration and reducing the influence of device mismatch near the decision threshold.

The performance gains are striking. Post-layout simulations evaluated across three process corners and five temperatures from minus 55 degrees Celsius to 125 degrees Celsius show that the proposed threshold logic achieves a maximum rising and falling offset voltage of just 9 millivolts. The conventional design, by contrast, exhibits a rising offset as high as 27 millivolts at the fast process corner at elevated temperature, with a strongly asymmetric falling offset. This improved symmetry and consistency means the new neuron can reliably generate a logic-one output for differential input voltages as small as 6.3 millivolts, enabling accurate decisions even in near-threshold conditions where conventional designs fail.

On the energy front, the results are equally compelling. The ACN achieves more than 90 percent total synapse energy savings, corresponding to an improvement factor of over 12 times, relative to an equivalent non-adiabatic CMOS capacitive neuron across operating frequencies from 500 kilohertz to 100 megahertz. The energy savings arise because adiabatic dissipation scales with the ratio of capacitance to the power-clock ramping time: the gentler the voltage ramp, the less energy is lost per cycle. The team also found that maximum energy dissipation occurs at intermediate input patterns rather than when all inputs are active, a departure from the monotonic behavior of their earlier architecture, and that actual operating frequency varies by only about 2 percent with changing capacitive loads.

Statistical robustness was verified through a 1000-sample Monte Carlo analysis incorporating both global process variation and local mismatch, using low-discrepancy sampling for uniform coverage of the parameter space. The analysis confirmed consistent energy savings exceeding 90 percent in the synapse energy profile. Interestingly, the adiabatic neuron’s energy distribution is right-skewed rather than normally distributed, reflecting the conditional and nonlinear nature of charge recovery, where small variations in threshold voltage or timing can asymmetrically degrade recovery efficiency and produce rare high-energy outliers. Even the worst-case samples in the long tail of the adiabatic distribution still outperformed the non-adiabatic equivalent, whose energy distribution was confirmed to be normal.

Supply voltage scaling provides a further lever for energy reduction. Because adiabatic energy dissipation depends on the product of effective resistance, capacitance, and ramping time, lowering the supply voltage reduces both the power-clock generator losses and the adiabatic losses themselves. The simulations show sustained energy savings above 90 percent under voltage scaling for all test vectors except the all-zero input condition, where no synapse switching occurs and the residual dissipation comes solely from the power-clock generator. Functionality is preserved throughout the scaling range, demonstrating that the design tolerates the shifting balance between switch on-resistances and supply levels.

The researchers position the ACN as a practical step toward energy-efficient neural network front-ends, particularly for feature-extraction stages in transfer learning applications where fixed, or baked-in, weights are acceptable. Because the design supports negative weights natively, fewer neurons may be needed overall to achieve the same functional performance compared with architectures restricted to positive weights. Looking ahead, the team notes that emerging memcapacitor devices, with their tunable capacitance, could replace the fixed metal-insulator-metal capacitor arrays, opening a path toward reconfigurable adiabatic neural hardware. Challenges remain, including comparator offset, noise, and metastability at high speeds, which the authors flag as priorities for future investigation. But with more than 90 percent energy savings verified across process, voltage, and temperature corners, the adiabatic capacitive neuron demonstrates that the energy bill of artificial intelligence can be paid in a fundamentally cheaper currency.

Subject of Research: An energy-efficient adiabatic capacitive neuron circuit for artificial neural network hardware

Article Title: Adiabatic capacitive neuron: an energy-efficient functional unit for artificial neural networks

Article References: Maheshwari, S., Smart, M., Raghav, H. S., Prodromakis, T., & Serb, A. (2026). Adiabatic capacitive neuron: an energy-efficient functional unit for artificial neural networks. Frontiers in Electronics, 7, Article 1743265. https://doi.org/10.3389/felec.2026.1743265

Image Credits: AI Generated

DOI: 10.3389/felec.2026.1743265

Keywords: adiabatic logic, artificial neural networks, capacitive synapses, energy-efficient computing, threshold logic, CMOS, neuromorphic hardware, charge recovery, binary neural networks, low-power design, Monte Carlo analysis, voltage scaling