The underlying problem is well known to memory engineers. Crossbar arrays, in which memory elements sit at the intersections of perpendicular word lines and bit lines, offer the most compact possible memory layout and can be stacked in three dimensions. But in a passive crossbar without a selector, current sneaks through neighboring unselected cells along paths known as sneak currents, corrupting the readout of the intended cell. Selectors are two-terminal devices placed in series with each memory element—forming one-selector-one-resistor or one-selector-one-capacitor cells—to suppress these parasitic currents. An ideal selector must be extremely nonlinear, passing large current only at its selected operating voltage while blocking current at half or a fraction of that voltage, yet it must also survive trillions of switching cycles, respond in nanoseconds, remain stable across temperatures and operate identically from device to device. No single selector technology has satisfied all of these requirements simultaneously.

The USC-led team’s answer is a graded tunnel barrier realized entirely within a van der Waals heterostructure. Instead of a single uniform insulating barrier, the device stacks materials of different band alignments so that the effective barrier profile changes with applied voltage. At low voltages, the barrier remains thick and high, strangling leakage current to negligible levels. As the voltage across the device rises toward the read or write condition, the barrier is thinned and lowered in a controlled fashion, allowing electrons to tunnel through with high efficiency. The result is an exponential increase in current over a small voltage window—precisely the nonlinearity that crossbar selectors demand.

To move beyond trial and error, the researchers developed a theoretical model that predicts the electrical characteristics of selectors with graded tunnel barriers. Guided by this model, they designed and fabricated two specific device structures. In the first, the primary tunnel barrier is hexagonal boron nitride, the wide-bandgap insulator often called white graphene. In the second, the barrier is gallium sulfide, a layered semiconductor with a smaller bandgap. Both variants sandwich the barrier between two layers of molybdenum disulfide, with graphene sheets serving as the top and bottom electrodes, forming the complete five-layer stack graphene/molybdenum disulfide/barrier/molybdenum disulfide/graphene.

The performance of the hexagonal boron nitride device is striking. It exhibits a nonlinearity exceeding 10 million, meaning the current at the operating voltage is more than ten million times larger than the leakage current at reduced voltages—among the highest values reported for any two-terminal selector. Perhaps more impressive is its endurance: the device survived more than a trillion switching cycles without failure, a figure that dwarfs the lifetimes of many competing selector technologies and approaches what commercial memory products require. Switching occurs in less than 20 nanoseconds, the current-voltage characteristics show minimal temperature dependence, and the variation from one device to another is low—critical attributes for manufacturing, where billions of cells must behave nearly identically.

The gallium sulfide variant trades some nonlinearity for a dramatically reduced operating voltage. Because gallium sulfide has a smaller barrier height than hexagonal boron nitride, the device can deliver a nonlinearity above one million while operating at only 2.5 volts. Low-voltage operation matters enormously for modern memory, which must integrate with silicon circuitry whose supply voltages continue to shrink. A selector that requires high voltages to turn on forces the surrounding periphery circuitry to handle elevated stress; a selector that switches at 2.5 volts eases that burden and reduces overall energy consumption during write operations.

Beyond single devices, the team demonstrated that their selectors can be integrated into functional memory cells. They built one-selector-one-resistor cells by pairing the selectors with memristive devices, including a hafnium-oxide-based memristor stack with palladium electrodes, and they also demonstrated one-selector-one-capacitor configurations. This dual compatibility with both resistive nonvolatile memory and capacitive volatile memory suggests the selector technology is genuinely universal, applicable across different memory families rather than tied to a single cell type. The researchers benchmarked their devices against the broad landscape of existing selector technologies—including ovonic threshold switching chalcogenides, niobium oxide threshold devices, metal-insulator-metal tunnel diodes and mixed-ionic-electronic-conduction access devices—and found that the van der Waals approach uniquely combines high selectivity with trillion-cycle endurance, nanosecond speed, temperature stability and low variability.

Choosing van der Waals materials is central to the achievement. These layered crystals are held together by weak interlayer forces, so each atomic plane can be exfoliated and restacked like molecular building blocks without the dangling bonds and interfacial defects that plague conventional three-dimensional semiconductors. Atomically sharp interfaces mean the tunnel barrier thickness is controlled layer by layer, giving designers reproducible, deterministic barrier profiles. Graphene electrodes contribute their own advantages, providing chemically inert, highly conductive contacts that do not interdiffuse with the underlying layers. The same properties that have made van der Waals heterostructures a playground for condensed matter physics here translate directly into manufacturable device metrics: negligible cycling variation, minimal temperature dependence and good interdevice uniformity all flow from the crystalline perfection of the interfaces.

The implications extend toward the long-sought goal of three-dimensional memory stacking. Because the entire selector is built from vertically stacked two-dimensional layers, it is inherently stackable, unlike selectors that rely on complex oxide growth or electroforming processes that are difficult to repeat layer upon layer. Paired with scalable nonvolatile memories such as memristors and phase-change or resistive cells, these selectors could enable dense three-dimensional crossbar memories for storage-class memory, in-memory computing and neuromorphic artificial intelligence hardware, where analog crossbar arrays perform vector-matrix multiplications directly in hardware. The research team, whose work was supported by the Army Research Office, the Air Force Office of Scientific Research and the National Science Foundation, has also released the experimental and simulation data through the Harvard Dataverse, giving the broader community the tools to build on the design framework. As the demand for data storage and energy-efficient computation continues its relentless climb, devices that tame sneak currents with atomic precision may prove to be one of the quiet enablers of the next memory generation.

Subject of Research: Van der Waals tunnel-junction selector devices with graded tunnel barriers for high-density memory crossbar arrays

Article Title: High-performance tunnel-junction selectors with graded tunnel barriers based on five-layer van der Waals heterostructures

Article References: High-performance tunnel-junction selectors with graded tunnel barriers based on five-layer van der Waals heterostructures. (n.d.). https://doi.org/10.1038/s41928-026-01704-2

Image Credits: AI Generated

DOI: 10.1038/s41928-026-01704-2

Keywords: van der Waals heterostructures, tunnel-junction selector, memory crossbar arrays, molybdenum disulfide, hexagonal boron nitride, gallium sulfide, memristors, nonlinearity, endurance, three-dimensional memory, nanoelectronics, Nature Electronics

The recent advances in 2D transistor technology are driven by innovations in several pivotal areas. One of the most significant breakthroughs has been in contact engineering, where researchers are making strides in minimizing contact resistance at the interface between the metal contacts and the 2D semiconductor. This is a crucial factor because high contact resistances can severely diminish the performance of scaled transistors. In conjunction with this, the scaling of channel lengths (L_CH) has been achieved to unprecedented levels, making it possible to fabricate transistors that are not only smaller but also more efficient.

The effective integration of high-κ gate dielectrics has further bolstered transistor performance. By reducing the equivalent oxide thickness (EOT) to less than 2.5 nm, researchers are able to enhance gate control over the channel, significantly lowering off-state leakage currents. Traditionally, negative threshold voltage values in 2D materials have posed a challenge, leading to undesirable off-state currents. However, recent developments have made it possible to engineer positive threshold voltages while keeping off-state currents below the critical threshold of 10 pA µm⁻¹.

A growing body of literature suggests that a monolayer-centric approach may not fully harness the advantages of few-layer materials. By shifting focus to bilayer and trilayer MoS₂ transistors, researchers have observed performance improvements that could reshape the landscape of semiconductor technology. In particular, trilayer MoS₂ transistors are showing remarkable enhancements in terms of on-state current and lower Schottky barrier heights. The ability to fine-tune the channel thickness allows for better charge transport properties and reduced scattering, leading to superior electrical performance.

Recent findings highlight the manufacturing feasibility of scaling MoS₂ transistors down to impressive dimensions of 35 nm for channel length and 30 nm for contact length. This level of scaling is not merely an academic pursuit; it has implications for real-world applications in ultra-low-power electronics. The achievement of approximately 1,000 scaled devices demonstrates the reliability and reproducibility of the approach, which is crucial for transitioning from lab-scale prototypes to industry-ready solutions.

This intensive research effort culminated in the successful fabrication of MoS₂ transistors that operate with on-state currents reaching 220 µA µm⁻¹. Notably, these devices achieve a positive threshold voltage, which facilitates design considerations for future applications in logic and memory technologies. When compared to their monolayer counterparts, trilayer MoS₂ devices provide a compelling alternative that combines the benefits of increased channel thickness with minimized resistance.

As momentum builds in the field of 2D materials, the questions about scalability, integration, and performance become increasingly relevant. Researchers and engineers are now tasked with understanding how to optimize the balance between these parameters to achieve the vision of next-generation transistors. The versatility of few-layer MoS₂ can potentially revolutionize applications in areas such as flexible electronics, high-frequency devices, and even optoelectronics.

While challenges remain in the form of contact resistance and the integration of high-quality dielectrics, the advancements made to date suggest a paradigm shift in how we conceptualize transistor structures. The continuous exploration of the properties of MoS₂ is paving the way for devices that can outperform traditional silicon-based technologies. This shift not only promises to address the scaling limits of silicon but also opens up new avenues for innovation in the tech industry.

Another area of investigation involves the long-term stability and reliability of MoS₂ transistors. As electronic devices become increasingly complex and performance-driven, ensuring that these 2D materials can withstand environmental stresses is essential. The progress seen in achieving reproducible device yields suggests that stability will not be a significant hindrance in the deployment of these transistors on a commercial scale.

The implications of this research extend beyond mere academic interest; the quest for new materials is driven by the industry’s need for more efficient, compact, and sustainable solutions. The use of MoS₂ could potentially lead to reduced energy consumption and lower operational costs, which are paramount concerns for manufacturers. Furthermore, the adoption of scalable fabrication techniques compatible with existing processes enhances the viability of transitioning from research to commercial production.

As this research continues to unfold, it will undoubtedly influence the design paradigms and material choices in semiconductor fabrication. The interplay between material properties, device architecture, and processing techniques remains a critical focus for researchers aiming to realize the full potential of 2D materials in commercial electronics. The future of the semiconductor industry may well be shaped by the innovations stemming from the study of materials like molybdenum disulfide.

The quest for ever-smaller, higher-performing electronic components continues unabated. With the successful demonstration of low-dimensional materials like MoS₂, the groundwork has been laid for further exploration of similar compounds and structures. The technology not only challenges the status quo but invites an entire generation of scientists and engineers to rethink and redesign the fundamentals of electronic circuitry for an era defined by miniaturization and efficiency.

With the convergence of material science, electrical engineering, and nanotechnology, the horizon for 2D materials like MoS₂ looks promising. This research not only represents a step forward in addressing the limitations of silicon-based technology but also serves as a beacon for future investigations into advanced materials that could redefine industry standards.

In conclusion, the development of high-performance molybdenum disulfide transistors with channel and contact lengths less than 35 nm showcases the tremendous potential of 2D materials. Their unique properties and ability to integrate with existing semiconductor technologies make them a compelling candidate for the future of electronics, promising performance enhancements that could enable more powerful, compact, and efficient devices. As research progresses, the possibilities for the application of MoS₂ and other 2D materials seem limitless, ushering in a new chapter in the evolution of semiconductor technology.

Subject of Research: Molybdenum disulfide transistors

Article Title: High-performance molybdenum disulfide transistors with channel and contact lengths below 35 nm.

Article References:

Sakib, N.U., Chen, C., Ding, L. et al. High-performance molybdenum disulfide transistors with channel and contact lengths below 35 nm.
Nat Electron (2025). https://doi.org/10.1038/s41928-025-01499-8

Image Credits: AI Generated

DOI: https://doi.org/10.1038/s41928-025-01499-8

Keywords: Molybdenum disulfide, Transistors, Two-dimensional materials, Semiconductor technology, Miniaturization, Contact engineering, High-κ dielectrics, On-state current, Electrical performance, Scalable fabrication.

The integration of 2D materials into transistors is hindered by the absence of compatible high-k dielectrics, essential for optimal channel control. The characteristics of 2D materials, such as their high surface-to-volume ratio and exceptional electronic properties, provide significant advantages; however, they also necessitate the development of new fabrication processes that can accommodate their distinct physical and chemical properties. Researchers have begun to scrutinize the effectiveness of existing silicon-based gate stack technologies to evaluate how they can be adapted or re-engineered to work harmoniously with 2D materials.

One of the most promising avenues of exploration involves ferroelectric-embedded gate stacks. These structures present additional capabilities that could revolutionize the development of non-volatile memory technologies. By embedding ferroelectric materials within the gate stack, researchers can leverage their unique switching properties to create devices that retain information even when powered down. Such innovations could further decouple memory from processing units, leading to new forms of logic-in-memory architectures that integrate storage and computation more seamlessly than ever before.

As the push for more efficient low-power transistors intensifies, the need for advanced gate stack strategies becomes paramount. Unlike traditional semiconductors, 2D materials can enable significantly lower power operations due to their unique electrical characteristics. In particular, high mobility in 2D materials signifies that transistors built from these substances can operate effectively at much lower voltages, reducing overall power consumption and heat generation.

However, achieving reliable performance in 2D transistors through effective gate stack engineering is a multifaceted challenge. The performance metrics for any transistor must not only include current drive capabilities but also highlight the importance of subthreshold swing, short-channel effects, and off-state leakage currents. Each of these factors plays a crucial role in determining how well a transistor can function, especially in the context of high-speed operations. Careful benchmarking against existing silicon technologies is essential to provide a framework for evaluation, paving the way for identifying performance gaps that need addressing.

Alongside technical performance, user-oriented aspects, such as scalability and manufacturing feasibility, present critical challenges to the widespread adoption of 2D transistors. The refinement of existing fabrication methods to support new materials is an arduous task that demands collaboration across multiple disciplines—ranging from materials science to electrical engineering. As such, advancements in gate stack engineering are not solely a scientific challenge but a manufacturing one as well, requiring innovative approaches that can accommodate a shift from silicon-centric methodologies toward those supportive of a new class of materials.

In addition to practical considerations, researchers are grappling with material stability and reliability over time. The interactions between 2D materials and their dielectric counterparts—whether they be ferroelectric or otherwise—must be meticulously understood to ensure consistent performance over prolonged use. Addressing degradation processes and stability issues will be pivotal before these next-generation transistors can be considered viable alternatives in commercial applications.

As investigations into the realm of 2D materials forge ahead, the International Roadmap for Devices and Systems lays out ambitious targets that the technology must meet. Commitments to solidify industry benchmarks require a continual reassessment of how experimental findings translate into real-world performance. The potential for 2D materials in various applications, including mobile devices, wearable technology, and even large-scale computing solutions, keeps researchers focused on the horizon of what’s possible.

The future of electronics may well hinge on the refinement and implementation of gate stack engineering strategies that can seamlessly incorporate 2D materials. Upcoming works in the field are expected to address not only technical barriers but also regulatory and economic aspects governing the manufacturing processes. As we edge closer to a post-silicon world, the collective effort in furthering this research will undoubtedly culminate in a new era of high-performance, low-power electronic devices.

As we stand on this pivotal brink of technological evolution, the prospect of utilizing 2D materials in transistor designs ignites a sense of excitement within the scientific community. Researchers are optimistic that, through persistent investigation and innovation, the integration of advanced gate stack engineering with novel materials will redefine the landscape of electronic devices in ways previously imagined only in theoretical studies. It is a tantalizing journey into the future, where every breakthrough in gate stack technology not only emboldens the progress of 2D materials but also leads us toward overcoming the limitations of traditional silicon technologies.

In summary, while challenges abound, the potential benefits presented by 2D materials in electronics are staggering. The era of enhanced computing capabilities and radically improved energy efficiency is on the horizon. A future filled with devices that outperform current technologies and harness the unique properties of 2D materials awaits—one that will ultimately redefine how we interact with technology daily.

Subject of Research: Gate Stack Engineering for Two-Dimensional Transistors

Article Title: Gate Stack Engineering of Two-Dimensional Transistors

Article References:

Kim, Y.H., Lee, D., Huh, W. et al. Gate stack engineering of two-dimensional transistors.
Nat Electron 8, 770–783 (2025). https://doi.org/10.1038/s41928-025-01448-5

Image Credits: AI Generated

DOI: https://doi.org/10.1038/s41928-025-01448-5

Keywords: Two-dimensional materials, Gate stack engineering, Transistors, Silicon technologies, Ferroelectric materials, Logic-in-memory, Low-power electronics.

Silicon’s dominance in the semiconductor industry is underpinned by decades of technological refinement centered around miniaturization, yet inevitable scaling challenges—ranging from short-channel effects to heat dissipation—have spurred the search for novel materials and architectures. Two-dimensional materials such as molybdenum disulfide (MoS₂) and tungsten diselenide (WSe₂) offer compelling advantages, including atomically thin channels ideal for electrostatic control and high carrier mobilities that surpass silicon in certain contexts. Yet, integrating these materials into complementary logic circuits, essential for power-efficient and high-performance digital electronics, has remained a significant hurdle, primarily due to difficulties in wafer-scale synthesis, doping control, and contact engineering.

Addressing these challenges head-on, the team engineered a CMOS platform by heterogeneously integrating large-area n-type MoS₂ and p-type WSe₂ field-effect transistors (FETs). This heterogeneous approach leverages the unique electronic properties of each material, enabling effective complementary operation. To optimize device performance, careful scaling of channel length and the adoption of a high-κ gate dielectric material were implemented. These design strategies were crucial for tailoring threshold voltages across both n-type and p-type transistors, ensuring that the devices operate efficiently and minimize leakage currents, which are detrimental to power consumption and overall circuit stability.

A key achievement of this research lies in the demonstration of robust device characteristics at scaled dimensions. Through precise material growth protocols and meticulous postprocessing techniques, the researchers attained transistor configurations that deliver high drive currents while suppressing subthreshold leakage. This balance is vital since the drive current dictates the switching speed and processing capability, whereas leakage currents impact power efficiency—a central consideration for any scalable semiconductor technology aiming to compete with established silicon processes.

The integrated 2D CMOS circuits exhibited functional operation below 3 volts, a testament to the meticulous engineering of device interfaces and gating architectures. The realized circuits achieved switching frequencies reaching up to 25 kHz, an impressive figure constrained predominantly by parasitic capacitances inherent in the device layout and fabrication processes. Although this frequency lags behind silicon microprocessors, it represents a pioneering proof of concept that validates the viability of 2D materials in practical computational hardware.

Noteworthy is the remarkably low power consumption observed in the 2D OISC system, operating in the picowatt range, coupled with energy-per-switching-event as low as approximately 100 picojoules. Such ultra-low power characteristics are highly desirable for applications demanding energy efficiency, including wearable electronics, implantable biomedical devices, and ubiquitous sensor networks. In these contexts, the ability to perform computations without significant power overhead could enable a new class of persistent, autonomous systems.

The authors did not stop at experimental demonstration. They further developed a comprehensive SPICE-compatible BSIM-BULK model calibrated with empirical device data, including variability across multiple transistor samples. By incorporating these realistic device-to-device variations, the modeling efforts provided invaluable insights into the scalability and practical performance bounds of the 2D material-based CMOS circuits. When benchmarked against state-of-the-art silicon microelectronics, the projections suggest that while current performance does not yet rival traditional silicon solutions, continuous material and processing improvements could close this gap, heralding a new era of 2D electronics.

This study epitomizes the complex interplay between advanced materials synthesis, device physics, and circuit design. Achieving complementary operation with two distinct 2D semiconductors required overcoming numerous technical barriers, including uniform wafer-scale crystal growth, controllable doping levels, and the formation of low-resistance, thermally stable contacts. The successful co-integration of n-type MoS₂ and p-type WSe₂ FETs on a common substrate signals a critical step toward scalable manufacturing processes compatible with existing silicon fab infrastructure.

From a broader perspective, this advance invites a reevaluation of long-standing paradigms in semiconductor technology, particularly as industry demands increasingly push beyond silicon’s fundamental limits. The ability to engineer and integrate atomically thin materials at wafer scale opens exciting frontiers not only for logic electronics but also for optoelectronics, flexible devices, and sensors. The modularity of 2D materials offers tantalizing prospects for heterogeneous integration with other emerging platforms, potentially fostering hybrid architectures that leverage the best attributes of multiple material systems.

Importantly, the research highlights the practical significance of device variability and interface engineering in 2D electronics. The authors’ approach in modeling and benchmarking accounts for real-world nonidealities, which is essential to translating lab-scale breakthroughs into industrial applications. Furthermore, the adopted high-κ gate dielectric, alongside efforts in threshold voltage tuning, illustrates how traditional semiconductor engineering principles must be adapted and refined for atomically thin materials.

The prototype one instruction set computer implemented in this work embodies a minimalist yet fully functional computing architecture, which, despite its simplicity, demonstrates the essential building blocks of digital logic implemented through 2D semiconductor technology. Its successful operation at ultra-low voltages and power levels underscores the inherent advantages of 2D materials for energy-efficient electronics while serving as a scalable platform for more complex integrated circuits.

While significant challenges remain —including improving operating frequency, enhancing device uniformity, and integrating with complementary fabrication techniques—the demonstrated system forms a pivotal foundation for future explorations in 2D microelectronics. It sparks optimism within the scientific community, signifying that 2D material-based complementary circuits may soon transition from academic curiosities to practical technologies integrated into everyday electronic devices.

In summation, the work by Ghosh and colleagues not only affirms the potential of 2D materials as viable alternatives to silicon in CMOS logic but also represents a landmark in the field’s evolution. By successfully synthesizing, engineering, and integrating large-area MoS₂ and WSe₂ transistors into a functional computing architecture, they have illuminated a promising path forward for the semiconductor industry. With continued research and development, the vision of ultra-scaled, energy-efficient 2D material-based microprocessors may well materialize, radically reshaping the landscape of electronics.

Subject of Research: Complementary CMOS circuits based on two-dimensional n-type MoS₂ and p-type WSe₂ field-effect transistors for logic computing.

Article Title: A complementary two-dimensional material-based one instruction set computer.

Article References:
Ghosh, S., Zheng, Y., Rafiq, M. et al. A complementary two-dimensional material-based one instruction set computer. Nature 642, 327–335 (2025). https://doi.org/10.1038/s41586-025-08963-7

Image Credits: AI Generated

DOI: https://doi.org/10.1038/s41586-025-08963-7