FAU team models energy efficiency at the processor level, wins 2018 Gauss Award
Researchers from the Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU) were awarded the 2018 Gauss Award during the opening session of ISC18 in Frankfurt, Germany. The award, which recognizes the most outstanding research paper presented during the annual conference, comes with a €3,000 prize and a keynote talk about the paper during the conference. This is the tenth consecutive year that the Gauss Centre for Supercomputing (GCS) has sponsored this award at ISC.
<p>Johannes Hofmann, computer scientist at FAU, led the research and was on site to receive the award.
"Winning this award helps make our research more visible to the [HPC] community," Hofmann said. "We hope this award encourages researchers to make use of the model and the best-practices recommended in the paper, and also hope it attracts other researchers to help expand the model."
The team's award-winning paper, titled "On the Accuracy and Usefulness of Analytic Energy Models for Contemporary Multicore Processors," focused on improving the accuracy of the ECM performance model and a multicore power model to better describe energy properties of processors commonly used in HPC resources.
Multi-core performance estimates of the original ECM model were based on linear scaling of single-core performance until a shared bottleneck (such as memory bandwidth) that limits performance is hit. In the improved ECM model, shared bottlenecks are modeled to better reflect Little's Law, which states that increased utilization of a resource (such as the memory bus) leads to a decrease in throughput, or processing rate. Among other things, the power model was extended to deal with shared bottlenecks as well. These improvements provide a more accurate view of processors' actual performance under circumstances realistic to the high computational demands of high-performance computing.
In its paper, the team studied performance, power, and energy properties of three different processor microarchitectures commonly used in HPC systems–Intel Sandy Bridge-EP, Broadwell-EP, and AMD Epyc. Using the improved models, the team was able to identify the optimal operating points with respect to both highest performance and the lowest energy-to-solution cost.
Hofmann indicated that as HPC systems become larger and even more complex, this type of research will be essential for ensuring that HPC centres minimize their environmental impact and offer researchers guidance to optimize their codes to make the best of use of a particular system's architecture.
"While increasing processor complexity is nothing new, the fact that a lot of the complexity is now exposed to the user is a new trend," Hofmann said. "We expect this trend to continue, and as a consequence, it will become increasingly difficult for users and programmers to choose the ideal setting for their applications without assistance from specialists or models."
The team presented its paper at ISC18 on Monday, June 25 at 5:30. More information can be found here: https://www.isc-hpc.com/awards-2018.html